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  • 02월 19일 10시 이후 : 초록수정 불가능, 일정확인 및 검색만 가능

제121회 대한화학회 학술발표회, 총회 및 기기전시회 안내 Controlling the Crystallization of Small Molecule Organic Semiconductors using Solution Shearing and their Application to Field-effect Transistors

2018년 2월 14일 17시 21분 41초
MAT2-2 이곳을 클릭하시면 발표코드에 대한 설명을 보실 수 있습니다.
금 09시 : 25분
Material Chemistry - Material Chemistry for Emerging Large Area Electronic Application
저자 및
Materials Science and Engineering, Korea Advanced Institute of Science and Technology, Korea

The electronic properties of solution-processable small molecule organic semiconductors (OSCs) have rapidly improved in recent years, rendering them highly promising for various low-cost large area electronic applications. Practical applications of organic electronics as field-effect transistors require sufficient field-effect mobility (1-10 cm2/Vs), patterned and precisely registered OSC film within the transistor channel, and device-to-device uniformity over a large area, a task that remains a significant challenge. Here we present solution shearing as a promising technique to achieve such a task. In solution shearing, organic solution is sandwiched between a heated substrate and a shearing blade. As the shearing blade moves, meniscus is formed through which solute deposits on the substrate to form a thin film. When the evaporation rate of the solvent at the meniscus matches that of the shearing rate, the crystals can be grown along the direction of shearing, resulting in aligned crystalline films. To further enhance crystallinity, the substrate can be patterned with alternation solvent wetting and dewetting regions, to limit nucleation events and impede lateral crystal growth. This resulted in high aligned crystals TIPS-pentacene with mobility as high as 2.7 cm2/Vs. Furthermore, we have developed a novel technique known as CONNECT (Controlled OSC NucleatioN and Extension for CircuiTs), which utilizes a non-wetting substrate with wetting electrodes to generate aligned organic films that were self-patterned and self-registered within the channel region, resulting in low device-to-device variability. We have fabricated transistor density as high as 840 dpi, with a yield of 99%. We have successfully built various logic gates and a 2-bit half adder circuit, demonstrating the practical applicability of our technique for large-scale circuit fabrication.